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this product conforms to specifications per the terms of the ramtron ramtron international corpor ation standard warranty. the product has completed ramtrons internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545 - fram, (719) 481 - 7000 http://www.r amtron.com rev. 3 .0 oct . 20 12 page 1 of 14 fm 22ld16 4mbit f - ram memory features 4mbit ferroelectric nonvolatile ram ? organized as 256kx16 ? configurable as 512kx8 using /ub, /lb ? 10 14 read/write cycles ? nodelay? writes ? page mode operation to 4 0mhz ? advanced high - reliability ferroelectric process sra m compatible ? jedec 256kx16 sram p inout ? 55 ns access time, 110 ns cycle time advanced features ? software programmable block write protect superior to battery - backed sram modules ? no b attery c oncerns ? monolithic r eliability ? true s urface m ount s olution, n o r ework s teps ? superior for m oisture, s hock, and v ibration low power operation ? 2.7v C 3.6v power supply ? low standby current (90a typ . ) ? low active current ( 8 ma typ.) industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 48 - ball green/r ohs fbga package ? pin compatible with fm21ld16 (2mb) and fm23mld16 (8mb) description the fm 22ld16 is a 256kx16 nonvolatile memory that reads and writes like a standard sram. a ferroelectric random access memory or f - ram is nonvolatile, which means that da ta is retained after power is removed. it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery - backed sram (bbsram). fast write timing and high write endur ance make the f - ram superior to other types of memory. in - system operation of the fm 22ld16 is very similar to other ram devices and can be used as a drop - in replacement for standard sram. read and write cycles may be triggered by /ce or simply by changin g the address. the f - ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm 22ld16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an sram . the fm 22ld16 includes a l ow voltage monitor that blocks access to the memory array when v dd drops below v dd min . the memory is protected against an inadvertent access and data corruption under this condition. the device also features software - controlled write protection. the memo ry array is divided into 8 uniform blocks, each of which can be individually write protected. the device is available in a 48 - ball fbga package. device specifications are guaranteed over industrial tem perature range C 40c to +85c. pin configuration top view (ball down) ordering information fm 22ld16 - 55 - bg 55 ns access, 48 - ball green/rohs fbga fm22ld16 - 55 - bgtr 55 ns access, 48 - ball green/rohs fbga , tape & reel / l b / o e a 0 a 1 a 2 n c d q 8 / u b a 3 a 4 / c e d q 0 d q 9 d q 1 0 a 5 a 6 d q 1 d q 2 v s s d q 1 1 a 1 7 a 7 d q 3 v d d v d d d q 1 2 n c a 1 6 d q 4 v s s d q 1 4 d q 1 3 a 1 4 a 1 5 d q 5 d q 6 d q 1 5 n c a 1 2 a 1 3 / w e d q 7 n c a 8 a 9 a 1 0 a 1 1 n c 1 2 3 4 5 6 a b c d e f g h
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 2 of 14 figure 1. block diagram p in description pin name type pin description a(17:0) input address inputs: the 18 address lines select one of 262,144 words in the f - ram array. the lowest two address lines a(1:0) may be used for page mode read and write operations. /ce input chip enabl e input: the device is selected and a new memory access begins when /ce is low . the entire address is latched internally on the falling edge of /c e. subsequent changes to the a(1 :0) address inputs allow page mode operation when /ce is low. /we input write enable: a write cycle begins when /we is asserted. the rising edge causes the fm 22ld16 to write the data on the dq bus to the f - ram array. the falling edge of /we latch es a new column address for page mode write cycles . /oe input output enable: when /o e is low, the fm 22ld16 drives the data bus when valid read data is available. deasserting /oe high tri - states the dq pins. dq(15:0) i/o data: 16 - bit bi - directional data bus for accessing the f - ram array. /ub input upper byte select: enables dq(15:8) pins during reads and writes. deasserting /ub high tri - states the dq pins. if the user does not perform byte writes and the device is not configured as a 512kx8, the /ub and /lb pins may be tied to ground. /lb input lower byte select: enables dq(7:0) pins d uring reads and w rites. deasserting /lb high tri - states the dq pins. if the user does not perform byte writes and the device is not configured as a 512kx8, the /ub and /lb pins may be tied to ground. vdd supply supply voltage vss supply ground a d d r e s s l a t c h & w r i t e p r o t e c t c e c o n t r o l l o g i c w e b l o c k & r o w d e c o d e r a ( 1 7 : 2 ) a ( 1 : 0 ) i / o l a t c h & b u s d r i v e r o e d q ( 1 5 : 0 ) 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k 3 2 k x 1 6 b l o c k a ( 1 7 : 0 ) . . . c o l u m n d e c o d e r . . . u b , l b 2
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 3 of 14 functio nal truth table 1,2 /ce /we a(17:2) a(1:0) operation h x x x standby/idle ? h v v read l h no change change page mode read l h change v random read ? l v v /ce - controlled write l ? v v /we - controlled write 2 l ? ? no change v page mode write 3 ? x x x starts precharge notes: 1) h=logic high, l=logic low, v=valid data, x=dont car e. 2) /we - controlled write cycle b egins as a read cycle and a(17:2 ) is latched then . 3) addresses a( 1 :0) must remain stable for at least 1 0 ns during page mode operation . 4) for write c ycles, data - in is latched on the rising edge of /ce or /we, whichever comes first. byte select truth table /oe /lb /ub operation h x x read; outputs disabled x h h l h l read; dq(7:0) hi - z l h read; dq(15:8) hi - z l l read x h l write; mask dq(7: 0) l h write; mask dq(15:8) l l write t he /ub and /lb pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 512kx8.
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 4 of 14 overview the fm 22ld16 is a wordwide f - ram memory logically organized as 262,144 x 16 and accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation which provides higher speed access to addresses within a page (row). an ac cess to a different page requires that either /ce transitions low or the upper address a(17:2) changes. memory operation users access 262,144 memory locations, each with 16 data bits through a parallel interface. the f - ram array is organized as 8 blocks ea ch having 8192 rows. each row has 4 column locations, which allows fast access in page mode operation. once an initial address has been latched by the falling edge of /ce, subsequent column locations may be accessed without the need to toggle /ce. when /c e is deasserted high, a precharge operation begins. writes occur immediately at the end of the access with no delay. the /we pin must be toggled for each write operation . the write data is stored in the nonvolatile memory array immediately, which is a fea ture unique to f - ram called nodelay tm writes. read operation a read operation begins on the falling edge of /ce. the falling edge of /ce causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus aft er the access time has been satisfied. once the address has been latched and the access completed, a new access to a random location (different row) may begin while /ce is still low. the minimum cycle time for random addresses is t rc . note that unlike sra ms, the fm 22ld16 s /ce - initiated access time is faster than the address cycle time. the fm 22ld16 will drive the data bus when /oe and at least one of the byte enables (/ub, /lb) is asserted low. the upper data byte is driven when /ub is low, and the lower data byte is driven when /lb is low. if /oe is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is deasserted high, the data bus will remain in a high - z state. write operation writes occur in th e fm 22ld16 in the same time interval as reads. the fm 22ld16 supports both /ce - and /we - controlled write cycles. in both cases, the address a(17:2) is latched on the falling edge of /ce . in a /ce - controlled write, the /we signal is asserted prior to beginn ing the memory cycle. that is, /we is low when /ce falls. in this case, the device begins the memory cycle as a write. the fm 22ld16 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when /ce is deas serted high. in a /we - controlled write, the memory cycle begins on the falling edge of /ce. the /we signal falls some time later. therefore, the memory cycle begins as a read. the data bus will be driven if /oe is low, however it will hi - z once /we is asse rted low. the /ce - and /we - controlled write timing cases are shown in the electrical specifications section. write access to the array begins on the falling edge of /we after the memory cycle is initiated. the write access terminates on the rising edge o f /we or /ce, whichever comes first. a valid write operation requires the user to meet the access time specification prior to deasserting /we or /ce. data setup time indicates the interval during which data cannot change prior to the end of the write acces s ( rising edge of /we or /ce ). unlike other truly nonvolatile memory technologies, there is no write delay with f - ram . since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the f - ram array is organized as 8 blocks each having 8192 rows. each row has 4 column addre ss locations. address inputs a(1:0) define the column address to be accessed. an access can start on any column address, and other column locations may be accessed without the need to toggle the /ce pin. for fast access reads, once the first data byte is driven onto the bus, the column address inputs a(1:0) may be changed to a new value. a new data byte is then driven to the dq pins no later than t aa p , which is less than half the initial read access time. for fast access writes, the first write pulse def ines the first write access. while /ce is low, a subsequent write pulse
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 5 of 14 along with a new column address provides a page mode write access . precharge operation the precharge operation is an internal condition in which the state of the memory is being prepa red for a new access. precharge is user - initiated by driving the /ce signal high. it must remain high for at least the minimum precharge time t pc . precharge is also activated by changing the upper addess a(17:2). the current row is first closed prior to accessing the new row. the device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and the new read data is valid within the t aa address access time. refer to the read cycle timing 1 diag ram on page 10. likewise a similar sequence occurs for write cycles. refer to the write cycle timing 3 diagram on page 12. the rate at which random addresses can be issued is t rc and t wc , respectively. software write protection the 256kx16 address space i s divided into 8 sectors (blocks) of 32kx16 each. each sector can be individually software write - protected and the settings are nonvolatile. a unique address and command sequence invokes the write protection mode. to modify write protection, the system ho st must issue six read c ommands, three write commands , and a final read command . the specific sequence of read addresses must be provided in order to access to the write protect mode. following the read address sequence, the host must write a data byte tha t specifies the desired protection state of each sector. for confirmation, the system must then write the complement of the protection byte immediately following the protection byte. any error that occurs including read addresses in the wrong order, issui ng a seventh read address, or failing to complement the protection value will leave the write protection unchanged. the write protect state machine monitors all addresses, taking no action until this particular read/write sequence occurs. during the addr ess sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. any address that occurs out of sequence will cause the software protection state machine to start over. after the address se quence is completed, the next operation must be a write cycle. the data byte contains the write - protect settings. this value will not be written to the memory array, so the address is a dont - care. rather it will be held pending the next cycle, which must be a write of the data complement to the protection settings. if the complement is correct, the write protect settings will be adjusted. if not, the process is aborted and the address sequence starts over. the data value written after the correct six addr esses will not be entered into memory. the protection data byte consists of 8 - bits, each associated with the write protect state of a sector. the data byte must be driven to the lower 8 - bits of the data bus, dq(7:0). setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. the following table shows the write - protect sectors with the corresponding bit that controls the write - protect setting. write protect sectors C 32k x16 blocks sector 7 3ffffh C 38000h sector 6 37ff fh C 30000h sector 5 2ffffh C 28000h sector 4 27fffh C 20000h sector 3 1ffffh C 18000h sector 2 17fffh C 10000h sector 1 0ffffh C 08000h sector 0 07fffh C 00000h the write - protect read address sequence follows: 1. 24 555h * 2. 3 aaaah 3. 0 2 333h 4. 1cccch 5. 0 00ffh 6. 3e f00h 7. 3 aaaah 8. 1cccch 9. 0ff00h 10. 00000h * if /ce is low enteri ng the sequence, then an address of 00000h must p recede 24 555h . the address sequence provides a very secure way of modifying the protection. the write - protect sequence has a 1 in 3 x 10 3 2 chance of random l y accessing exactly the 1 st six addresses . the odds are further reduced by requiring three more write cycles, one that requires an exact inversion of the data byte. a flow chart of the entire write protect operati on is shown in figure 2. the write - protec t settings are non volatile. the factory default: all blocks are unprotected.
fm22ld16 - 256kx16 fram rev. 3 .0 o c t . 20 12 page 6 of 14 figure 2. write - protect state machine for example, the following sequence write - protects addresses from 18000h to 27fffh (sectors 3 & 4): addres s data read 24 555h - read 3 aaaah - read 02 333h - read 1cccch - read 0 00ffh - read 3e f00h - write 3 aaaah 18h ; bits 3 & 4 = 1 write 1cccch e7h ; complement of 18h write 0ff00h - ; data is dont care read 00000h - ; return to normal operation n o r m a l m e m o r y o p e r a t i o n r e a d 2 4 5 5 5 h ? r e a d 3 a a a a h ? a n y o t h e r o p e r a t i o n r e a d 0 2 3 3 3 h ? r e a d 1 c c c c h ? r e a d 0 0 0 f f h ? r e a d 3 e f 0 0 ? h o l d d a t a b y t e w r i t e 1 c c c c ? d a t a c o m p l e m e n t ? y n n n n n y y y y y n y w r i t e 3 a a a a ? y w r i t e 0 f f 0 0 ? y n r e a d 0 0 0 0 0 ? e n t e r n e w w r i t e p r o t e c t s e t t i n g s n r e a d 1 a a a a ? w r i t e 1 c c c c ? y d r i v e w r i t e p r o t e c t d a t a o u t r e a d 0 0 0 0 0 ? n y n c h a n g e w r i t e p r o t e c t s e t t i n g s r e a d w r i t e p r o t e c t s e t t i n g s s e q u e n c e d e t e c t o r
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 7 of 14 software write protect timing sram drop - in replacement the fm 22ld16 has been designed to be a drop - in replacement for standard asynchronous srams. the device does not require /ce to toggle for each new address. /ce may remain low indefinitely. while /ce is low, the device automatically detects address chan ges and a new access is begun. this functionality allows /ce to be grounded as you might with an sram. it also allows page mode operation at speeds up to 40 mhz. note that if /ce is tied to ground, the user must be sure /we is not low at powerup or powerdown events. if /ce and /we are both low during power cycles, data corruption will occur. figure 3 shows a pullup resistor on /we which will ke ep the pin high during power cycles assuming the mcu/mpu pin tri - states during the reset condition. the pullup resistor value should be chosen to ensure the /we pin tracks v dd yet a high enough value that the current drawn when /we is low is not an issue. a 10kohm resistor draws 330ua when /we is low and v dd =3.3v. figure 3. use of pullup resistor on /we note: if /ce is tied to ground, the user gives up the ability to perform the software write - protect sequence. for applicatio ns that require the lowest power consumption, the /ce signal should be active only during memo ry accesses. the fm 22ld16 draws supp ly current while /ce is low, even if addresses and control signals are static. while /ce is high, the device draws no more th an the maximum standby current i sb . the fm 22ld16 is backward compatible with the 1mbit fm20l08 and 256kbit fm18l08 devices. that is , operating the fm 22ld16 with /ce toggling low on every address is perfectly acceptable. the /ub and /lb byte select pin s are active for both read and write cycles. they may be used to allow the device to be wired as a 512kx8 memory. the upper and lower data bytes can be tied together and controlled with the byte selects. individual byte enables or the next higher address line a(18) may be available from the system processor. figure 4 . fm 22ld16 wired as 512kx8 ce we oe a(17:0) dq fm22ld16 v dd mcu/ mpu r c e a ( 1 7 : 0 ) w e d q ( 1 5 : 0 ) 2 4 5 5 5 d a t a d a t a o e 0 2 3 3 3 1 c c c c 0 0 0 f f 3 e f 0 0 3 a a a a 1 c c c c 0 f f 0 0 0 0 0 0 0 3 a a a a d q ( 1 5 : 8 ) d q ( 7 : 0 ) d ( 7 : 0 ) a ( 1 7 : 0 ) / c e / u b / l b / w e / o e 4 m b i t f - r a m f m 2 2 l d 1 6 a ( 1 8 ) a ( 1 7 : 0 )
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 8 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4 . 5 v v in voltage on any signal pin with respect to v ss - 1.0v to + 4 . 5 v and v in < v dd +1v t stg storage temperature - 55 ? c to +125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model ( jede c std jesd22 - a114 - d) - charged device model ( jede c std jesd22 - c101 - c) - machine model (jedec std jesd22 - a115 - a) 2.5kv 1.5kv 150v package moisture sensitivity level msl - 3 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings condit ions for extended periods may affect device reliability. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 2.7 3.3 3.6 v i dd power supply current 8 1 2 ma 1 i sb standby current @ t a = 25 c @ t a = 85 c 90 - 1 5 0 270 ? ? li input leakage current ? ? lo output leakage current ? ? ih input high voltage 2.2 v dd + 0.3 v v il input low voltage - 0.3 0.6 v v oh 1 output high volta ge ( i oh = - 1.0 ma) 2.4 v v oh2 output high voltage ( i oh = - 100 ? a) v dd - 0.2 v v ol1 output low voltage ( i ol = 2.1 ma) 0.4 v v ol2 output low voltage ( i ol = 100 ? a) 0.2 v notes 1. v dd = 3.6v, /ce cycling at min. cycle time. all inputs toggling at c mos levels (0.2v or v dd - 0.2v) , all dq pins unloaded. 2. v dd = 3.6v, /ce at v dd , all other pins are static and at cmos levels (0.2v or v dd - 0.2v) . 3. v in , v out between v dd and v ss .
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 9 of 14 read cycle ac parameters (t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6v unless other wise specified) symbol parameter min max units notes t rc read cycle time 110 - ns t ce chip enable access time - 55 ns t aa address access time - 110 ns t oh output hold time 20 - ns t aap page mode address access time - 25 ns t ohp page mode output hold time 5 - ns t ca chip enable active time 55 - ns t pc precharge time 55 - ns t ba /ub, /lb access time - 2 0 ns t as address setup time (to /ce low) 0 - ns t ah address hold time (/ce - controlled) 55 - ns t oe output enable access time - 15 ns t hz chip enable to output high - z - 10 ns 1 t ohz output enable high to output high - z - 10 ns 1 t bhz /ub, /lb high to output high - z - 10 ns 1 write cycle ac parameters (t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min max units notes t wc write cycle time 110 - ns t ca chip enable active time 55 - ns t cw chip enable to write enable high 55 - ns t pc precharge time 55 - ns t pwc page mode write enable cycle time 2 5 - ns t wp write enable pulse width 16 - ns t as address setup time (to /ce low) 0 - ns t asp page mode address setup time (to /we low) 8 - ns t ahp page mode address hold time (to /we low) 15 - ns t wlc write enable low to /ce high 25 - ns t b lc /ub, /lb low to /ce high 25 - ns t wla write enable low to a(17:2) change 25 - ns t awh a(17:2) change to write enable high 110 - ns t bs /ub, /lb setup time (to /ce low) 2 - ns t bh /ub, /lb hold time (to /ce high) 0 - ns t ds data input setup time 14 - ns t dh data input hold time 0 - ns t wz write enable low to output high z - 10 ns 1 t wx write enable high to output driven 10 - ns 1 t ws write enable to /ce low setup time 0 - ns 2 t wh write enable to /ce high hold time 0 - ns 2 notes 1 this parameter is characterized but not 100% tested. 2 the relationship between /ce and /we determines if a /ce - or /we - controlled write occurs. the parameters t ws and t wh are not tested. capacitance (t a = 25 ? c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacit ance (dq) - 8 pf c in input capacitance - 6 pf
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 10 of 14 power cycle timing (t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min max units notes t pu power - up (after v dd min. is reached) to first access time 45 0 - ? s t p d last write (/we high) to power down time 0 - ? s t v r v dd rise time 5 0 - ? s/v 1 ,2 t v f v dd fall time 100 - ? s/v 1 ,2 notes 1 sl ope measured at any point on v dd waveform . 2 ramtron cannot test or characterize all v dd power ramp profiles . the beh avior of the internal circuits is difficult to predict when v dd is below the level of a transistor threshold voltage . ramtron st r ongly recommends that v dd power up faster than 100ms through the range of 0. 4 v to 1.0v. data retention ( v dd = 2.7v to 3.6v) parameter mi n units notes data retention 10 years ac test conditions input pulse levels 0 to 3v input and output timing levels 1.5v input rise and fall times 3 ns output load capacitance 30pf read cycle timing 1 (/ce low, /oe low) read cycle timing 2 (/ce - controlled) a ( 1 7 : 0 ) t r c t a a p r e v i o u s d a t a v a l i d d a t a t o h v a l i d d a t a t r c t a a t o h d q ( 1 5 : 0 ) a ( 1 7 : 0 ) d q ( 1 5 : 0 ) t a s t h z t o e t o h t o h z u b / l b o e c e t b a t b h z t c a t p c t a h t c e
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 11 of 14 page mode read cycle timing although sequential column addressing is shown, it is not required. write cycle timing 1 (/we - controlled) note: /oe (not sh own) is low only to show effect of /we on dq pins write cycle timing 2 (/ce - controlled) c e a ( 1 7 : 2 ) o e d q ( 1 5 : 0 ) t a s t c a a ( 1 : 0 ) t o e t c e t o h z t a a p t o h p t h z t p c d a t a 0 d a t a 1 d a t a 2 c o l 0 c o l 1 c o l 2 t b h d i n c e a ( 1 7 : 0 ) w e t c a t p c d q ( 1 5 : 0 ) t w p t c w t a s d o u t d o u t t d s t d h t w x t w z t h z t w l c u b / l b t b s c e a ( 1 7 : 0 ) w e d q ( 1 5 : 0 ) t w s t a s t w h t d h t d s d i n t c a t p c u b / l b t b l c
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 12 of 14 write cycle timing 3 (/ce low ) note: /oe (not shown) is low only to show effect of /we on dq pins page mode write cycle timing although sequential column addressing is shown, it is not required. power cycle timing d i n a ( 1 7 : 0 ) w e d q ( 1 5 : 0 ) t w c t d h t w l a t d s t a w h d o u t d o u t t w z t w x d i n c e a ( 1 7 : 2 ) w e t c a t p c d q ( 1 5 : 0 ) t c w a ( 1 : 0 ) c o l 0 c o l 1 d a t a 0 c o l 2 t a s t d s d a t a 1 t w p t d h d a t a 2 o e t a h p t p w c t w l c t a s p v d d m i n . v d d w e t p d c e d q r / w a l l o w e d t p u d i n v d d m i n . d o u t
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 13 of 14 mechanical drawing 4 8 - ball fbga (0.75mm ball pitch ) refer to jedec jep95 for complete dimensions and notes. note: all dimensions in millimeters . 48 fbga package marking scheme legend: xxxxxx= part number, s=speed, p=package llllll= l ot code, yy=year, ww=work week examples: fm22ld16 , green/rohs fbga package, lot c8556953bg1, year 2008, work week 44 ramtron fm22ld16 - 55 - bg c8556953bg1 0844 ramtron x xxxxxx - s - p lllllll yyww p i n a 1 6 . 0 0 b s c 1 . 2 0 m a x 0 . 1 0 m m 1 . 8 7 5 8 . 0 0 b s c 0 . 2 5 6 . 0 0 b s c 0 . 4 0 0 . 0 5 0 . 7 5 t y p t o p v i e w b o t t o m v i e w a b c d e f g h 6 5 4 3 2 1
fm22ld16 - 256kx16 fram rev . 3 .0 oct . 2 012 page 14 of 14 revision history revision date summary 1.0 10/ 2 / 20 08 initial release. 1.1 2/ 18/2009 added ub/lb signals to timing diagrams and added timing parameters to ac table. added tape & reel ordering information. 2.0 12/22/2009 changed status to pre - production. lowered i dd limit. added ub/lb signals to timing diagrams and added timing par ameters to ac table. expanded explanation of precharge operation. updated lead temperature rating in abs max table. removed v tp spec. added tape & reel ordering information. 3.0 1 0/ 9 /2012 moved to production status.

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